Workshop Description

Hands‑on introduction to UVM testbench architecture, reusable components, and verification strategies for FPGA/SoC designs. 

The emphasis is on: 

• Introducing structured verification planning and coverage‑driven methodology 

• Covers complete UVM architecture, including agents, sequences, and phasing 

• Builds practical skills in drivers, monitors, scoreboards, and TLM connections 

• Explains factory, configuration database, and testbench reuse mechanisms 

• Implements constrained random stimulus and layered sequence libraries 

• Integrates UVM Register Abstraction Layer (RAL) for register‑level verification 

• Applies functional coverage and regression strategies for closure 

• Includes hands‑on labs targeting real SoC subsystems (AXI, Avalon, DMA, interrupts, CDC)

Workshop Duration: 2 days