Advanced VHDL for Verification
Experienced VHDL writers who wish to take their use of the language to a higher level in the areas of behavioral modeling and verification.
This workshop is aimed at experienced VHDL users who wish to take their use of the language to a higher level. The workshop is a mix of lecture and lab-exercises.
The focus is on:
- Using behavioral modeling techniques to develop VHDL-based scoreboards and predictor models
- Using new capabilities included in recent updates of VHDL for verification
- Applying advanced stimulus-related techniques such as random stimulus generation and LFSRs
- Applying advanced analysis and scoreboarding techniques such as MISR signatures and monitors
- Increasing automation and productivity by using makefiles and version control systems
SystemVerilog for Verification
Engineers interested in applying SystemVerilog technology to their verification process.
This workshop introduces engineers to developing verification environments using SystemVerilog. The workshop covers the new basic features in SystemVerilog such as extended data types, array types, extensions to tasks and functions and dynamic processes. The workshop teaches Object Oriented Program (OOP) modeling using SystemVerilog classes and shows how to create OOP testbenches and connect them to your DUT. New SystemVerilog techniques such as constrained randomization for stimulus generation and covergroups and assertions for analysis are covered as well as how to apply them to your OOP testbench. A good portion of time will be spent applying principles learned in lecture to hands-on labs.
The emphasis is on:
- Using the new data types, array types, and structures in testbenches
- Using dynamic processes to create parallel stimulus
- Creating OOP style testbenches using OOP techniques
- Applying SystemVerilog constrained randomization to testbench stimulus generation
- Creating covergroups to apply functional coverage to the analysis portion of a testbench
- Creating assertions for testing DUT logic
- Binding assertions to a DUT without modifying the DUT
- Learning how to use the Universal Verification Methodology (UVM) library
Design or Verification Engineers who wish to deploy SystemVerilog Assertions.
This workshop is targeted towards Design and Verification engineers who wish to deploy Assertion-based Verification within their next project.
Assertion-based Verification is becoming a cornerstone of good design and verification practice. SystemVerilog is one of the first languages to feature a 100% native temporal assertion syntax, making it extremely well integrated with the language. Our course stresses a methodical approach to learning and developing good coding style.
The focus is on:
- Explaining how assertions can help you in your design or verification code
- Explaining and deploy the most useful SVA constructs
- Writing a broad range of SystemVerilog Assertions
- Using the bind directive to incorporate Assertions into design code at runtime
Engineers with UVM experience who want to take their skills to the next level to be able to tackle real world problems.
This workshop is designed for UVM users who want to take their skills to the next level and address testbench issues. Putting together real world testbenches requires more than just knowing the components of the UVM library. Real world testbenches have issues that require knowing how to apply the UVM library to solve these issues. Issues such as multiple interfaces to the DUT, layering stimulus, concurrent process synchronization, dealing with behaviors such as interrupts, reset and multiple response types, and building scalable, reusable testbenches are addressed. In this Advanced UVM class, you will gain experience in dealing with these and other testbench challenges. The class works through various testbench issues and challenges providing solutions. You will be able to apply these solutions to your testbench. You will also take away from this class detailed real world example testbenches that illustrate solutions to issues providing a great reference in doing your testbench. A good deal of this class is spent in interactive discussion, “whiteboarding,” and applying the topics to the student’s application.
The emphasis is on:
- Creating scalable, reusable UVM testbench structures
- Dealing with thorny issues such as reset, interrupts, and synchronization across multiple components
- Applying advanced stimulus related techniques such as layered stimulus or complex scenarios
- Applying advanced analysis techniques such as scoreboard draining
- Applying advanced register integration and techniques to your register model