Verification
Verification is a critical phase in digital design that ensures your hardware behaves as intended—before it’s implemented in silicon or on an FPGA. In these sessions, learners will explore the principles and practices of verifying digital systems through simulation, testbenches, and assertions.
Advanced VHDL for Verification
Target Audience
Experienced VHDL writers who wish to take their use of the language to a higher level in the areas of behavioral modeling and verification.
Description
This workshop is aimed at experienced VHDL users who wish to take their use of the language to a higher level. The workshop is a mix of lecture and lab-exercises.
The emphasis is on:
- Using behavioral modeling techniques to develop VHDL-based scoreboards and predictor models
- Using new capabilities included in recent updates of VHDL for verification
- Applying advanced stimulus-related techniques such as random stimulus generation and LFSRs
- Applying advanced analysis and scoreboarding techniques such as MISR signatures and monitors
- Increasing automation and productivity by using makefiles and version control systems
SystemVerilog for Verification
Target Audience
Hardware verification engineers and FPGA designers with Verilog experience looking to advance into SystemVerilog-based verification.
Description
Designed for experienced RTL users, this workshop introduces engineers to developing comprehensive verification environments using SystemVerilog and advances their language skills through a blend of lectures and hands-on lab exercises.
The emphasis is on:
- Introduces SystemVerilog for modern verification of complex digital designsCovers key language extensions beyond Verilog (data types, arrays, procedures)
- Develops Object-Oriented Programming (OOP) skills for scalable testbench design
- Builds layered, reusable verification environments using interfaces and TLM
- Applies constrained random stimulus generation for thorough design exploration
- Teaches functional coverage and coverage-driven verification techniques
- Explores assertion-based verification (SVA) for checking design intent
- Provides a foundation for UVM-based verification methodologies
SystemVerilog Assertions
Target Audience
Design and verification engineers with RTL experience who want to use assertions in simulation and formal flows.
Description
Designed for experienced HDL users, this workshop introduces engineers to developing comprehensive verification environments using SystemVerilog and advances their language skills through a blend of lectures and hands-on lab exercises.
The emphasis is on:
- Introducing Assertion‑Based Verification (ABV) and its role in modern verification
- Explains immediate and concurrent assertions with SystemVerilog syntax
- Builds practical skills in sequences, properties, and temporal expressions
- Covers clocking, reset handling, and multi‑clock domain assertions
- Demonstrates integration of assertions into simulation testbenches
- Applies assertions for functional coverage and protocol checking
- Introduces formal property verification (FPV) concepts and workflows
- Presents best practices for reusable assertion IP and sign‑off quality
Formal Verification: Applied
Target Audience
Verification and FPGA engineers with SystemVerilog/SVA experience who are ready to apply formal methods in real projects.
Description
Hands‑on introduction to formal verification using SVA, model checking, and practical tool flows to prove RTL correctness and find hidden bugs early.
The emphasis is on:
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Building foundational understanding of formal verification concepts and workflows
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Teaches how to write effective SystemVerilog Assertions for formal engines
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Introduces assume‑guarantee reasoning to constrain and guide formal analysis
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Covers bounded model checking, k‑induction, and IC3/PDR techniques
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Demonstrates counterexample debugging and root‑cause analysis
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Explores RTL‑to‑gate equivalence checking for design assurance
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Uses Questa Formal tools (PropCheck, AutoCheck) in hands‑on labs
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Shows how to integrate formal verification into a complete verification strategy and sign‑off flow
Formal Verification: Advanced
Target Audience
Experienced formal verification engineers ready to apply advanced techniques to real SoC‑level verification challenges.
Description
Advanced, hands‑on formal techniques for verifying complex SoC subsystems, interfaces, and CDC/RDC signoff using SystemVerilog Assertions and formal engines.
The emphasis is on:
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Building on foundational formal knowledge to address real SoC‑scale verification problems
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Applies formal methods to bus protocols (AXI, Avalon) and interface correctness
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Verifies full SoC integration, register maps, and system connectivity
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Covers CDC/RDC analysis and formal signoff methodologies
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Explores advanced datapath, arithmetic, and memory verification strategies
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Introduces security and information flow verification using formal techniques
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Uses abstraction and assume‑guarantee reasoning to scale proofs
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Drives end‑to‑end specification to signoff workflows with practical labs
UVM Fundamentals
Target Audience
Engineers new to UVM who want to transition from RTL design or basic testbenches into structured, production‑grade verification.
Description
Hands‑on introduction to UVM testbench architecture, reusable components, and verification strategies for FPGA/SoC designs.
The emphasis is on:
- Introducing structured verification planning and coverage‑driven methodology
- Covers complete UVM architecture, including agents, sequences, and phasing
- Builds practical skills in drivers, monitors, scoreboards, and TLM connections
- Explains factory, configuration database, and testbench reuse mechanisms
- Implements constrained random stimulus and layered sequence libraries
- Integrates UVM Register Abstraction Layer (RAL) for register‑level verification
- Applies functional coverage and regression strategies for closure
- Includes hands‑on labs targeting real SoC subsystems (AXI, Avalon, DMA, interrupts, CDC)
UVM Advanced
Target Audience
Experienced UVM engineers and SoC verification specialists ready to tackle large‑scale FPGA systems and advanced verification flows.
Description
Advanced UVM techniques for complex SoC FPGA verification, integrating formal methods, high‑performance testbenches, and real‑world subsystem validation.
The emphasis is on:
- Deepening UVM expertise with scalable, production‑grade verification architectures
- Designs complex testbench topologies for SoC FPGA (HPS, fabric, interconnects)
- Implements advanced sequencing, reuse, and multi‑agent coordination strategies
- Extends RAL usage for comprehensive register and memory verification
- Integrates SVA and formal verification into UVM‑based workflows
- Applies coverage‑driven methodologies with advanced closure strategies
- Optimizes simulation performance and prepares environments for emulation
- Covers real‑world IP (PCIe, EMIF, bridges) and subsystem‑level verification