Signal/Power Integrity

Gigabit Channel Design and Modeling

Target Audience

Engineers and designers who need to understand PCB signal and power integrity modeling.


In the gigabit (GB) regime, accurate serial link channel modeling is imperative for first time modeling success. At these speeds everything matters. Part of that success is understanding PCB fabrication nuances that will affect the accuracy of signal and power integrity modeling. In this workshop, attendees will learn about printed circuit (PCB) fabrication process and high-level design modeling techniques for first time project success.

The focus is on:

  • Signal Integrity/Power Integrity Primer
  • Transmission lines overview
  • Crosstalk and reflection mitigation best practices
  • Vias and stub effects
  • PCB fabrication process overview
  • PCB stackup best practices
  • Understanding fiberglass styles and how it affects GB channel performance
  • Fiber-weave issues and mitigation techniques
  • Conductor roughness and its effect on dielectric constant, characteristic impedance, phase delay and insertion loss
  • How to extract and apply the right material properties from manufacturers’ data sheets to use for successful stackup and high-speed channel modeling
  • Popular roughness models and how to get the right parameters for accurate loss modeling
  • Demystifying the Simonovich Cannonball model and how to apply it to determine roughness parameters for Huray model from data sheets alone
  • How to apply Cannonball parameters in popular field solvers.
  • Case study to compare simulated transmission line interconnect models with measurements