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Create a Customized Agenda

Home » Workshops » Create a Customized Agenda

Our Customized Agenda Module Selector functionality is still under construction. In the meantime, please contact us to discuss your needs and help you create a customized agenda.

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Versal ACAP

Programmable Logic PerspectiveNOCEmbedded Design PerspectiveAI EngineDesign ToolsBoot and Platform ManagementDebugging HardwareDevice InterfacesPower and Board Design

FPGA and ACAP Design Methodologies

FPGAs for ManagersUltraFast Design Methodology

Languages

VHDLVerilogSystemVerilog for DesignTCL

Device Architecture

Versal ACAPZynq UltraScale+ MPSoCRFSoCUltraScale/UltraScale+7-SeriesVirtex-6Spartan-6Spartan-6 Design Migration

Tools and Flows

Vivado Design SuiteVivado IP IntegratorVitis IDEVitis HLSPetaLinuxDynamic Function ExchangeModel Composer

Programmable Logic Design

Essentials of Programmable Logic DesignAdvanced Programmable Logic DesignAdvanced XDC and Timing AnalysisAdvanced Design TechniquesAdvanced Timing ClosureUltraFast Design MethodologyDebugging AMD-Xilinx Hardware Designs

Embedded Software Design

Adaptive SoCs for System ArchitectsBuilding Applications in MPSoCEmbedded Systems Design TechniquesOperating Systems and HypervisorsDesigning with PetaLinux

Algorithm Acceleration

Accelerating Software Applications in VitisAlgorithm OptimizationAccelerator Kernels Using Versal AIEngineAlveo Cards for Accelerate

DSP Design

DSP PrimerBuilding High Performance DSP Functions

System Design

Designing PCIe SystemsDeveloping AI Inference SolutionsDeveloping Multimedia SolutionsVision Based Applications with Kria

Verification

Advanced VHDL for VerificationSystemVerilog for VerificationSystemVerilog AssertionsUVM

Signal/Power Integrity

Gigabit Channel Design and Modeling

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