Languages
Understanding how key languages are used in digital hardware design and FPGA development, designers can efficiently describe, simulate, and implement robust digital systems tailored for both ASIC, SoC and FPGA targets.
Designing with VHDL
Target Audience
Design engineers who want to learn how to write synthesizable RTL code in VHDL as well as simple testbenches to verify the design at a block level.
Description
This comprehensive workshop covers everything from an introduction to the VHDL language through to advanced techniques to help write more robust and reusable code. New users may wish to subscribe to the entire workshop, while users with some experience may decide to choose only the modules where they feel a need to improve their knowledge and skills. This workshop is vendor agnostic, and the techniques may be applied to any target architecture. It focuses on teaching good RTL coding style for synthesis but also discusses basic testbench and verification techniques.
The emphasis is on:
- Writing efficient hardware designs
- Performing high-level HDL simulations
- Employing structural, register transfer level (RTL), and behavioral coding styles
- Targeting AMD Xilinx devices specifically and FPGA devices in general
- Utilizing best coding practices concepts and their architectures
- Writing efficient and reusable RTL, testbenches, and packages
- Creating self-testing testbenches
- Creating realistic models
- Using the text I/O capabilities of the VHDL language
- Storing simulation data dynamically
- Creating parameterized code for design reuse
- Writing testbenches
Designing with Verilog
Target Audience
Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs.
Description
This workshop provides a thorough introduction to the Verilog language.
The emphasis is on:
- Writing efficient hardware designs
- Performing high-level HDL simulations
- Employing structural, register transfer level (RTL), and behavioral coding styles
- Targeting AMD-Xilinx devices specifically and FPGA devices in general
- Utilizing best coding practices
Designing with SystemVerilog
Target Audience
Design engineers with Verilog experience who are interested in applying the synthesizable features of SystemVerilog and SystemVerilog Assertions to their designs.
Description
This workshop provides a thorough introduction to SystemVerilog constructs and features in SystemVerilog designed to capture design intent to allow Simulation tools to analyze for correct RTL design practices and speed up the design process.
Half of the workshop is devoted to SystemVerilog Assertions (SVA), with practical exercises to reinforce the material.
The emphasis is on:
- Evaluating the new RTL features in SystemVerilog and what they can bring to your design methodology
- Describing the new SystemVerilog features capable of capturing the designers intent in their RTL code
- Explaining how assertions can help you in your design or verification code
- Describing and deploying the most useful SVA constructs
- Writing a broad range of SystemVerilog Assertions
- Using the bind directive to incorporate Assertions into design code at runtime
- Reviewing new data types, structs, unions, arrays, procedural blocks, re-usable tasks, functions, and packages
- Targeting and optimizing Xilinx devices using SystemVerilog
Scripting with TCL
Target Audience
Engineers and designers who would like an introduction to the Tcl scripting language.
Description
Learn how to use Tcl syntax and language structures to build scripts suitable for use with EDA design tools. Learn about the effective use of variables, data types, and Tcl constructs to build effective conditional statements and loop controls.
The emphasis is on:
- Basic syntax and language structure of the Tcl language
- Executing Tcl commands from a command line script
- Understanding variables and data types
- How to use Tcl language constructs to build conditional statements and loop controls for some common FPGA applications
- Use of lists and arrays in efficient data structures
- Use of procedures, packages, and namespaces to develop modules and functions
Using Zephyr for AMD SoCs
Target Audience
Engineers and designers who want to use Zephyr to target AMD SoCs.
Description
Zephyr is used for building real-time operating systems (RTOS) that are optimized for AMD’s SoCs. It supports multiple hardware architectures and is designed for resource-constrained devices. Zephyr provides a full-stack embedded ecosystem that includes drivers, connectivity stacks, Devicetree-based hardware abstraction, and built-in tools for configuration, debugging, and testing. This makes it a versatile platform for embedded engineers working with AMD SoCs
The emphasis is on:
- Zephyr RTOS
- How to set up the Zephyr environment
- Creating a Vivado environment
- Generating a System Device Tree using XSA
- Setting up the Zephyr repository for a targeted hardware design
Designing with Python
Target Audience
Engineers and designers who want to leverage Python to effectively target AMD devices.
Description
The Python open-source programming language has become a de facto standard in applications ranging from engineering, scientific, data science, machine learning, information technology, and artificial intelligence. Leveraging Python productivity directly on the Zynq™ SoC and Versal™ Adaptive SoC architectures, users can exploit the benefits of programmable logic and microprocessors to more easily build designs for artificial intelligence, machine learning, and information technology applications.
The emphasis is on:
- Identify core aspects of programming and features of the Python language
- Understand and apply core programming concepts like data structures, conditionals, loops, variables, and functions
- Design and write fully functional Python programs using commonly used data structures, custom functions, and reading and writing to files
- Gain a solid understanding of algorithmic thinking, Python syntax, code testing, debugging techniques, and modular code development
- Apply Python programming logic, including variables, data structures, branching, loops, functions, objects, and classes
- Debugging and error handling
- Use of procedures, packages, and namespaces to develop modules and functions