Versal ACAP

Versal Programmable Logic Perspective

Target Audience

Software and hardware developers, system architects, and anyone who wants to learn about the architecture of the Versal ACAP device

Description

This workshop provides detailed information about the Versal® ACAP programmable logic architecture and design methodology.

The emphasis is on:

  • Reviewing the architecture of the Versal ACAP
  • Describing the different components available in the Versal architecture and what resources they contain
  • Utilizing the hardened blocks available in the Versal architecture
  • Using the provided design tools and methodology to create complex systems
  • Providing an overview of the network on chip (NoC) and AI Engine concepts and their architectures
  • Performing system-level simulation and debugging

Versal Network on Chip (NOC)

Target Audience

Hardware developers and system architects — whether migrating from existing AMD Xilinx devices or starting out with the Versal ACAP devices

Description

This workshop introduces the Versal® ACAP network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal ACAP device, the workshop provides a close examination of how the NoC is used to efficiently move data within the device.

The emphasis is on:

  • Enumerating the major components comprising the NoC architecture in the Versal ACAP
  • Implementing a basic design using the NoC
  • Configuring the NoC for efficient data movement

Versal Embedded Design Perspective

Target Audience

Software and hardware developers, system architects, and anyone who wants to learn about the architecture of the Versal ACAP device

Description

This workshop provides a detailed examination of the Versal® ACAP Processing System architecture and design methodology.

The emphasis is on:

  • An overview of the architecture of the Versal ACAP
  • Describing the different programmable engines available in the Versal architecture and what resources they contain
  • Understanding the dedicated IO and interfaces to the Processing System of the Versal architecture
  • Using the provided design tools and methodology to create embedded systems
  • Performing embedded design simulation and debugging

Versal AI Engine

Target Audience

Software and hardware developers, system architects, or anyone who needs to accelerate their software functions and algorithms using AMD-Xilinx devices

Description

This workshop provides a detailed description of the Versal® AI Engine architecture, including how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and AI Engines, and how to analyze the kernel program using various debugger features. It also demonstrates how to utilize the AI Engine APIs and advanced MAC intrinsics, AI Engine library for faster development and advanced features in adaptive data flow (ADF) graph implementation, such as using streams, cascade stream, buffer location constraints, runtime parameterization and APIs to update and read runtime parameters.

The emphasis of this workshop is on:

  • Illustrating the AI Engine architecture
  • Designing single AI Engine kernels using the Vitis™ unified software platform
  • Designing multiple AI kernels using data flow graphs with the Vitis IDE
  • Explaining the data movement between AI Engines via memory and DMA, and between AI Engines and programmable logic (PL)
  • Implementing a system-level design flow (PS + PL + AIE) and the supported simulation
  • Using an interface for data movement between the PL and AI Engine
  • Utilizing AI Engine APIs and advanced MAC intrinsics to implement filters
  • Utilizing the AI Engine library for faster development
  • Applying advanced features for optimizing a system-level design
  • Optimizing AI Engine kernels using compiler directives, programming style, and efficient movement of data
  • Describing C++ kernel template functionality
  • Identifying the different types of kernel instance states
  • Programming a FIR filter using AI Engine APIs
  • Debugging applications using the Vitis unified software platform

Versal Design Tools

Target Audience

Hardware designers, software engineers, and system architects who are interested in learning about design tools and flows to target all resources in Versal devices.

Description

This workshop provides a deep exploration into the Vivado® Design Suite, Vitis Integrated Design Environment, and other development tools for users who want to take full advantage of the Versal device feature set.

The emphasis is on:

  • Using the Vitis platform
  • Learning the Vitis HLS tool flow
  • Learning about Vivado Design Suite
  • Learning about different projects and project structure within AMD-Xilinx tools
  • Navigating and controlling the design through different mechanisms, including GUI, Tcl commands, hot keys, and menus
  • Creating a block design using the Vivado Design Suite
  • Creating a model-based design using HDL, HLS, and AIE library blocks along with custom blocks in Vitis Model Composer
  • Implementing DSP functions using Vitis Model Composer
  • Converting C/C++ designs into RTL implementations
  • Developing software applications using Vitis
  • Applying Xilinx Design Constraints
  • Implementing AMD-Xilinx IP
  • Creating custom IP via the IP packaging flow
  • Generating and reading and understanding reports
  • Debugging and profiling designs
  • Verifying and debugging AI Engine code using the Vitis analyzer
  • Simulating and debugging a complex system created using AI Engine library blocks
  • Cross-Triggering designs with both programmable logic and software components
  • Learning about synthesis options and how they may be used to control design results
  • Applying optimization techniques
  • Utilizing design implementation tools

Versal Boot and Platform Management

Target Audience

Software developers and system architects interested in understanding the boot process, including creating bootable images, platform management controller (PMC), and the platform loader and manager (PLM).

Description

This workshop provides a detailed examination of the tools and resources available for booting and configuring a Versal ACAP

The emphasis is on:

  • Reviewing OS implementation options, including hypervisors and various Linux implementations
  • Booting and configuring a system
  • Applying various power management techniques for the Versal ACAP
  • Understanding the platform management controller (PMC), platform loader and manager (PLM) software and boot and configuration
  • Understanding the various components of a boot image, including the configuration binaries (CDO), and the container file, or programmable device image (PDI)
  • Reviewing the system startup phases
  • Exploring the processes and differences in both the secure and non-secure boot flows

Debugging Versal Hardware

Target Audience

Hardware developers and system architects and anyone who wants to learn about the tools and techniques available to debug the Versal ACAP device

Description

This workshop provides an exploration into the tools and techniques available to debug the Versal™ ACAP, including features for debugging the fabric (programmable logic) and the hard blocks. The workshop also covers ChipScoPy APIs, which provide the Python interface to program and debug the Versal ACAP devices.

The emphasis is on:

  • Describing the Versal ACAP design flows
  • Enumerating the Versal ACAP debug features for programmable logic (PL) and hard block debugging
  • Debugging the Versal ACAP using different debug IP cores
  • Using ChipScoPy APIs for hardware debugging
  • Improving Versal ACAP system performance

Versal Device Interfaces

Target Audience

Hardware designers, software engineers, and system architects who want to learn more about Versal ACAP interfaces and IP, including memory interfaces, PCIe, and high speed serial transceivers.

Description

This workshop provides a system-level understanding of Versal® ACAP interfaces. Serial transceiver architecture, IP generation, simulation, and implementation are covered. Additional information on PCB design issues is also covered. A detailed investigation of the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal® architecture are included.

The focus is on:

  • Versal ACAP IO variations, electrical standards, and configuration
  • Memory interfaces and configurations
  • Versal ACAP serial transceivers
  • Versal IP for interfacing to external devices
  • Configuring Transceivers using the Wizard IPs
  • Using transceiver IP example designs
  • Simulating and implementing transceiver IPs
  • Identifying the advanced capabilities of the serial transceivers, including using IBERT and eye scan options
  • Accessing the appropriate reference material for board design issues involving signal integrity, the power supply, reference clocking, and trace design
  • Understanding Xilinx PCI Express design methodology
  • Enumerating various Xilinx PCI Express core products
  • Generating PCI Express example designs and simple applications
  • Identifying the advanced capabilities of the PCIe specification

Versal Power and Board Design

Target Audience

Hardware designers and system architects wanting to develop an effective power distribution network for the Versal ACAP

Description

This workshop provides a system-level understanding of power and thermal issues related to designing with the Versal® ACAP. PCB design considerations for the Versal ACAP are also covered.

The emphasis is on:

  • Estimating power using power analysis
  • Managing thermal design
  • Understanding Versal device packaging
  • Implementing proper pin-to-board connection
  • Using the Versal PCB Schematic Checklist to validate PCB design