Adaptive SoCs for System Architects
Target Audience
System architects interested in understanding the capabilities and ecosystem of the Zynq UltraScale+ MPSoC and Versal ACAP families.
Description
This workshop provides system architects with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC and Versal® ACAP families.
The emphasis is on:
- Utilizing power management strategies effectively
- Leveraging the platform management unit (PMU) capabilities
- Running the system securely and safely
- Reviewing the high-level architecture of the devices
- Identifying appropriate boot sequences
Building Applications in the Zynq UltraScale+ MPSoC Device
Target Audience
Hardware designers, software developers, and system architects interested in understanding the capabilities and ecosystem of the Zynq UltraScale+ MPSoC device
Description
This workshop provides a detailed examination of the Zynq® UltraScale+™ MPSoC family and the development methods required to design a custom embedded system.
The focus is on:
- An overview of the features and capabilities of the device
- Device configuration and implementation options
- Virtualization
- Options to configure and build embedded Linux OS
- Booting and configuring a system
- Safety & security, and power management
- Details of the processor system (PS)
- Interfaces between processor system (PS) and programmable logic (PL)
- Building software drivers for programmable logic peripherals
- Configuring RTOS
Embedded Systems Design Techniques
Target Audience
Engineers who are interested in developing embedded systems with the Zynq SoC, Zynq UltraScale+ MPSoC, Versal ACAP, and/or MicroBlaze soft processor core
Description
This workshop provides an examination of embedded concepts, tools, and techniques using the Vivado® Design Suite and Vitis™ unified software platform.
The emphasis is on:
- Designing, expanding, and modifying embedded systems utilizing the features and capabilities of the Zynq® System on a Chip (SoC), Zynq UltraScale+™ MPSoC, Versal® ACAP, and MicroBlaze™ soft processor
- Adding and simulating AXI-based peripherals using bus functional model (BFM) simulation
- Reviewing the Vitis tool
- Customizing board support packages (BSPs) for resource access and management of AMD Xilinx libraries
- Utilizing device drivers effectively
- Developing software applications for the available processors
- Debugging and integrating user applications
- Employing best practices to enable good design decisions
- Debugging Using Cross-Triggering
Operating Systems and Hypervisors
Target Audience
Software developers interested in understanding popular OS and hypervisor options and other high-level system design issues
Description
This workshop provides software developers options and techniques for selecting and implementing various types of operating systems and hypervisors on Zynq® UltraScale+™ MPSoC and Versal® ACAP devices.
The emphasis is on:
- Exploring the capabilities of the application processing unit (APU) and real-time processing unit (RPU) relative to performance improvement and OS implementation
- Reviewing the catalog of OS implementation options, including Arm® TrustZone technology, hypervisors, and various Linux implementations
- Applying various power management techniques for the Zynq UltraScale+ MPSoC and Versal ACAP families
Designing with PetaLinux
Target Audience
Embedded software developers interested in customizing a kernel using PetaLinux on the Arm processors available in AMD Xilinx SoCs
Description
This workshop provides embedded systems developers experience with creating an embedded Linux system targeting AMD Xilinx SoCs using the PetaLinux tools.
The emphasis is on:
- Using open-source embedded Linux components
- Using the PetaLinux tool design flow
- Creating and debugging an application
- Building the environment and booting the system using the Arm® processors available in AMD Xilinx SoCs
- Customizing the root file system
- Configuring the Linux environment and network components
- Developing custom hardware and custom drivers