Workshop Description

Advanced, hands‑on formal techniques for verifying complex SoC subsystems, interfaces, and CDC/RDC signoff using SystemVerilog Assertions and formal engines. 

The emphasis is on: 

• Building on foundational formal knowledge to address real SoC‑scale verification problems 

• Applies formal methods to bus protocols (AXI, Avalon) and interface correctness 

• Verifies full SoC integration, register maps, and system connectivity 

• Covers CDC/RDC analysis and formal signoff methodologies 

• Explores advanced datapath, arithmetic, and memory verification strategies 

• Introduces security and information flow verification using formal techniques 

• Uses abstraction and assume‑guarantee reasoning to scale proofs 

• Drives end‑to‑end specification to signoff workflows with practical labs 

Workshop Duration: 2 days