Tools and Flows
Modern FPGA, SoC and Adaptive SoC development relies on a suite of integrated tools and well-defined design flows to turn ideas into functional hardware and software systems.
Vivado Design Suite
Target Audience
Hardware designers, software engineers, and system architects who are interested in learning everything about the Vivado Design Suite tool.
Description
This workshop provides a deep exploration into the Vivado® Design Suite for users who want to take full advantage of the Vivado Design Suite feature set.
The emphasis is on:
- Learning about Vivado Design Suite projects
- Learning the different modes of operation
- Understanding the design flow
- Applying AMD Design Constraints (XDCs)
- Navigating and controlling the design through different mechanisms, including GUI, Tcl commands, hot keys, and menus
- Creating and understanding timing reports
- Learning about synthesis options and how they may be used to control design results
Designing with Vivado IP Intergator
Target Audience
Software and hardware developers, system architects, and anyone who wants to learn about the Vivado™ Design Suite IP Integrator tool.
Description
This workshop provides an exploration of the IP Integrator tool and its features to gain the expertise needed to develop, implement, and debug different IP Integrator block designs using the Vivado® Design Suite.
The emphasis is on:
- Creating an IP Integrator block design using the Vivado Design Suite
- Creating your own custom IP via the IP packaging flow
- Using the IP Integrator to add and configure the Versal™ Adaptive SoC CIPS block and then to export the generated programmable device image (PDI)
- Configuring the AXI network on chip (NoC) to access DDR memory controllers in Versal Adaptive SoC devices
- DFX Block Design Containers in IP Integrator
- Module Referencing in IP Integrator
Vitis™ Integrated Design Environment
Target Audience
Software engineers and embedded developers using AMD tools for software development.
Description
This workshop demonstrates the tools and techniques required for software design and development using the Vitis unified software platform.
The emphasis is on:
- Using the Vitis platform
- Learning about different projects and project structure within Vitis
- Migrating existing SDK projects to the Vitis platform
- Developing software applications using Vitis
- Generating and reading reports
- Debugging and profiling software designs
- Cross-Triggering designs with both programmable logic and software components
Vitis™ HLS
Target Audience
Software and hardware engineers looking to utilize high-level synthesis.
Description
This workshop provides a thorough exploration of the Vitis™ High-Level Synthesis (HLS) tool.
The emphasis is on:
- Converting C/C++ designs into RTL implementations
- Learning the Vitis HLS tool flow
- Creating I/O interfaces for designs by using the Vitis HLS tool
- Applying different optimization techniques
- Improving throughput, area, latency, and logic by using different HLS pragmas/directives
- Exporting IP that can be used with the Vivado IP catalog
- Downloading for in-circuit validation
PetaLinux
Target Audience
Embedded software developers interested in customizing a kernel using PetaLinux on the Arm processors available in AMD Xilinx SoCs.
Description
This workshop provides embedded systems developers experience with creating an embedded Linux system targeting AMD Xilinx SoCs using the PetaLinux tools.
The emphasis is on:
- Using open-source embedded Linux components
- Using the PetaLinux tool design flow
- Creating and debugging an application
- Building the environment and booting the system using the Arm® processors available in AMD Xilinx SoCs
- Customizing the root file system
- Configuring the Linux environment and network components
- Developing custom hardware and custom drivers
Dynamic Function Exchange (Partial Reconfiguration)
Target Audience
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who have need to understand Dynamic Function eXchange techniques.
Description
This workshop provides a detailed look at how to construct, implement, and download a Dynamic Function eXchange (DFX) FPGA design using the Vivado® Design Suite. This course covers both the tool flow and mechanics of successfully creating a DFX design.
The emphasis is on:
- Identifying best design practices and understanding the subtleties of the DFX design flow
- Using the DFX Controller and DFX Decoupler IP in the DFX process
- Implementing DFX in an embedded system environment
- Applying appropriate debugging techniques on DFX designs
- Employing best practice coding styles for a DFX system
Vitis™ Model Composer
Target Audience
System engineers, system designers, logic designers, and experienced hardware engineers who are implementing Versal AI Engine, HDL, and HLS algorithms using the MathWorks MATLAB and Simulink software and want to use Vitis Model Composer.
Description
This workshop provides experience with using the Vitis Model Composer tool for model-based designs.
The emphasis is on:
- Creating a model-based design using HDL, HLS, and AIE library blocks along with custom blocks in Vitis Model Composer
- Implementing DSP functions using Vitis Model Composer
- Utilizing design implementation tools
- Transforming algorithmic specifications to production-quality IP implementations using automatic optimizations and leveraging the high-level synthesis technology of the Vitis HLS tool
- Creating Versal™ AI Engine graphs and kernels using Vitis Model Composer
- Connecting AI Engine blocks and non-AI Engine blocks
- Verifying and debugging AI Engine code using the Vitis analyzer
- Simulating and debugging a complex system created using AI Engine library blocks
Using Yocto Project for AMD SoCs and Adaptive SoCs
Target Audience
Engineers and embedded system developers who want to use Yocto Project to customize Linux for AMD SoCs and Adaptive SoCs.
Description
This course focuses on the Versal Adaptive SoC and Zynq UltraScale+ MPSoC architectures
The emphasis is on:
- Introduction to embedded Linux and the Yocto Project
- Understanding Yocto components
- Build system configuration and the Yocto build workflow
- Understanding the concept of Yocto Layers and Recipes
- Reviewing BSPs and package groups and their functionality in the Yocto design flow