Versal ACAP
Target Audience
Software and hardware developers, system architects, and anyone who wants to learn about the architecture of the Versal ACAP device.
Description
This workshop provides detailed information about the Versal® ACAP architecture and design methodology.
The emphasis is on:
- Reviewing the architecture of the Versal ACAP
- Describing the different engines available in the Versal architecture and what resources they contain
- Utilizing the hardened blocks available in the Versal architecture
- Using the provided design tools and methodology to create complex systems
- Describing the network on chip (NoC) and AI Engine concepts and their architectures, implementing a basic design using the NoC, and configuring the NoC for efficient data movement
- Performing system-level simulation and debugging
- Understanding the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal® architecture
- Investigating the AI Engine architecture
- Identifying the advanced capabilities of the Versal ACAP serial transceivers
Zynq UltraScale+ MPSoC
Target Audience
System architects, hardware designers, and software developers interested in understanding the capabilities and ecosystem of the Zynq UltraScale+ MPSoC device.
Description
This workshop provides an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family.
The emphasis is on:
- Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)
- Reviewing the various power domains and their control structure
- Illustrating the processing system (PS) and programmable logic (PL) connectivity
- Utilizing QEMU to emulate hardware behavior
- Utilizing power management strategies effectively
- Leveraging the platform management unit (PMU) capabilities
- Running the system securely and safely
- Reviewing the high-level architecture of the devices
- Reviewing the catalog of OS implementation options, including hypervisors and various Linux implementations
- Identifying appropriate boot sequences
- Booting and configuring a system
RFSoC
Target Audience
Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ RFSoC data converter and SD-FEC hard blocks.
Description
This workshop provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.
The focus is on:
- Describing the RFSoC family in general
- Identifying applications for the RF Data Converter and SD-FEC blocks
- Configuring, simulating, and implementing the blocks
- Verifying the RF Data Converter on real hardware
- Reviewing power estimation to help identify the power demands of the RFSoC device in various operating modes
- Identifying proper layout and PCB considerations since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device
UltraScale/UltraScale+
Target Audience
Anyone who would like to build a design targeting the UltraScale or UltraScale+ device family.
Description
This workshop provides an introduction to the UltraScale™ and UltraScale+™ architectures.
The emphasis is on:
- Examining CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources
- Describing the dedicated transceivers and Transceiver Wizard
- Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities
- Migrating existing designs and IP to the UltraScale architecture with optimal use of the Vivado® Design Suite
7-Series
Target Audience
Hardware and firmware engineers who are interested in understanding how to effectively utilize and properly design targeting the primary architectural resources found in 7 series devices, and implement a system on a chip using the Zynq SoC and programmable logic.
Description
This workshop provides a detailed exploration of the 7 series architecture, including the Zynq-7000 family.
The focus is on:
- Utilizing 7 series CLB, clocking, memory, DSP, and I/O resources
- Describing the dedicated hardware resources available (PCI Express® technology, analog-to-digital converters, and gigabit transceivers)
- Employing proper HDL coding techniques to get the most out of device resources
- Identifying the features and benefits of the Zynq SoC architecture
- Describing the architecture of the Arm® Cortex™-A9 processor-based processing system (PS) and the connections to the programmable logic (PL)
- Detailing the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupts, and memory controllers
- Effectively accessing and using the PS DDR controller from PL user logic
- Interfacing PL-to-PS connections efficiently
- Employing best practice design techniques for implementing functions in the PS or PL
Virtex-6
Target Audience
Designers who are interested in designing with the Virtex-6 family of devices.
Description
This workshop supports both experienced and less experienced FPGA designers, as it also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA.
The focus of is on:
- Device overview
- CLB construction
- MMCM clocking resources
- Global, regional and I/O clocking techniques
- Memory, FIFO and DSP resources
- I/O and source-synchronous resources
- Soft memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology, and GTP transceivers) are also introduced.
Spartan-6
Target Audience
Designers who are interested in designing with the Spartan-6 family of devices.
Description
This workshop supports both experienced and less experienced FPGA designers, as it also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA.
The focus is on:
- Device overview
- CLB construction
- DCM and PLL clocking resources
- Global and I/O clocking techniques
- Memory and DSP resources
- I/O and source-synchronous resources
- Memory controller support and the dedicated hardware resources available in each of the sub-families (PCI Express® technology, memory controller block, and GTP transceivers) are also introduced.
Spartan-6 Design Migration
Target Audience
Architects, managers, FPGA designers, board designers, and anyone considering migrating Spartan-6 to a newer Xilinx architecture
Description
This workshop provides an overview of key points of consideration and specific guidance in migrating a Spartan-6 design to a newer Xilinx
target technology. There are many key differences targeting Spartan-6 including software flow, utilization of IP, constraining the design and
many more.
The focus is on:
- AMD-Xilinx 28nm and 16nm architectures
- Key differences between ISE and Vivado Design Suite
- ISE to Vivado Design Suite migration
- Software flow differences
- Comparing UCF constraints to XDC constraints
- IP migration
- Comparing CoreGen to IP Catalog
- Vivado Design Suite reports
- Baselining a design in Vivado Design Suite