Workshop Description

Advanced UVM techniques for complex SoC FPGA verification, integrating formal methods, high‑performance testbenches, and real‑world subsystem validation. 

The emphasis is on: 

• Deepening UVM expertise with scalable, production‑grade verification architectures 

• Designs complex testbench topologies for SoC FPGA (HPS, fabric, interconnects) 

• Implements advanced sequencing, reuse, and multi‑agent coordination strategies 

• Extends RAL usage for comprehensive register and memory verification 

• Integrates SVA and formal verification into UVM‑based workflows 

• Applies coverage‑driven methodologies with advanced closure strategies 

• Optimizes simulation performance and prepares environments for emulation 

• Covers real‑world IP (PCIe, EMIF, bridges) and subsystem‑level verification

Workshop Duration: 2 days