Workshop Description

Designed for experienced RTL users, this workshop introduces engineers to developing comprehensive verification environments using SystemVerilog and advances their language skills through a blend of lectures and hands-on lab exercises.

The emphasis is on:

• Introduces SystemVerilog for modern verification of complex digital designs
• Covers key language extensions beyond Verilog (data types, arrays, procedures)
• Develops Object-Oriented Programming (OOP) skills for scalable testbench design
• Builds layered, reusable verification environments using interfaces and TLM
• Applies constrained random stimulus generation for thorough design exploration
• Teaches functional coverage and coverage-driven verification techniques
• Explores assertion-based verification (SVA) for checking design intent
• Provides a foundation for UVM-based verification methodologies

Workshop  Duration: 3 days