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DTSTART;TZID=America/Halifax:20260908T110000
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DTSTAMP:20260728T013558Z
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UID:10000001-1788865200-1789059600@2rtp.com
SUMMARY:SystemVerilog for Verification
DESCRIPTION:Workshop Description \nDesigned for experienced RTL users\, this workshop introduces engineers to developing comprehensive verification environments using SystemVerilog and advances their language skills through a blend of lectures and hands-on lab exercises. \nThe emphasis is on: \n\nIntroduces SystemVerilog for modern verification of complex digital designs\nCovers key language extensions beyond Verilog (data types\, arrays\, procedures)\nDevelops Object-Oriented Programming (OOP) skills for scalable testbench design\nBuilds layered\, reusable verification environments using interfaces and TLM\nApplies constrained random stimulus generation for thorough design exploration\nTeaches functional coverage and coverage-driven verification techniques\nExplores assertion-based verification (SVA) for checking design intent\nProvides a foundation for UVM-based verification methodologies\n\nWorkshop  Duration: 3 days
URL:https://2rtp.com/workshop/systemverilog-for-verification/
CATEGORIES:Verification
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DTSTART;TZID=America/Halifax:20260929T110000
DTEND;TZID=America/Halifax:20261001T170000
DTSTAMP:20260728T013627Z
CREATED:20260722T152755Z
LAST-MODIFIED:20260728T013627Z
UID:10000002-1790679600-1790874000@2rtp.com
SUMMARY:SystemVerilog Assertions
DESCRIPTION:Workshop Description \nDesigned for experienced HDL users\, this workshop introduces engineers to developing comprehensive verification environments using SystemVerilog and advances their language skills through a blend of lectures and hands-on lab exercises.   \nThe emphasis is on:  \n\nIntroducing Assertion‑Based Verification (ABV) and its role in modern verification \n\n\nExplains immediate and concurrent assertions with SystemVerilog syntax \n\n\nBuilds practical skills in sequences\, properties\, and temporal expressions \n\n\nCovers clocking\, reset handling\, and multi‑clock domain assertions \n\n\nDemonstrates integration of assertions into simulation testbenches \n\n\nApplies assertions for functional coverage and protocol checking \n\n\nIntroduces formal property verification (FPV) concepts and workflows \n\n\nPresents best practices for reusable assertion IP and sign‑off quality \n\nWorkshop Duration: 3 days
URL:https://2rtp.com/workshop/systemverilog-assertions/
CATEGORIES:Verification
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Halifax:20261013T110000
DTEND;TZID=America/Halifax:20261014T170000
DTSTAMP:20260728T013647Z
CREATED:20260722T152746Z
LAST-MODIFIED:20260728T013647Z
UID:10000003-1791889200-1791997200@2rtp.com
SUMMARY:Formal Verification: Applied
DESCRIPTION:Workshop Description \nHands‑on introduction to formal verification using SVA\, model checking\, and practical tool flows to prove RTL correctness and find hidden bugs early.  \nThe emphasis is on:  \n\nBuilding foundational understanding of formal verification concepts and workflows \n\n\nTeaches how to write effective SystemVerilog Assertions for formal engines \n\n\nIntroduces assume‑guarantee reasoning to constrain and guide formal analysis \n\n\nCovers bounded model checking\, k‑induction\, and IC3/PDR techniques \n\n\nDemonstrates counterexample debugging and root‑cause analysis \n\n\nExplores RTL‑to‑gate equivalence checking for design assurance \n\n\nUses Questa Formal tools (PropCheck\, AutoCheck) in hands‑on labs \n\n\nShows how to integrate formal verification into a complete verification strategy and sign‑off flow\n\nWorkshop Duration: 2 days
URL:https://2rtp.com/workshop/formal-verification-applied/
CATEGORIES:Verification
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BEGIN:VEVENT
DTSTART;TZID=America/Halifax:20261027T110000
DTEND;TZID=America/Halifax:20261028T170000
DTSTAMP:20260728T013718Z
CREATED:20260722T152822Z
LAST-MODIFIED:20260728T013718Z
UID:10000004-1793098800-1793206800@2rtp.com
SUMMARY:Formal Verification: Advanced
DESCRIPTION:Workshop Description \nAdvanced\, hands‑on formal techniques for verifying complex SoC subsystems\, interfaces\, and CDC/RDC signoff using SystemVerilog Assertions and formal engines.  \nThe emphasis is on:  \n\nBuilding on foundational formal knowledge to address real SoC‑scale verification problems \n\n\nApplies formal methods to bus protocols (AXI\, Avalon) and interface correctness \n\n\nVerifies full SoC integration\, register maps\, and system connectivity \n\n\nCovers CDC/RDC analysis and formal signoff methodologies \n\n\nExplores advanced datapath\, arithmetic\, and memory verification strategies \n\n\nIntroduces security and information flow verification using formal techniques \n\n\nUses abstraction and assume‑guarantee reasoning to scale proofs \n\n\nDrives end‑to‑end specification to signoff workflows with practical labs \n\nWorkshop Duration: 2 days
URL:https://2rtp.com/workshop/formal-verification-advanced/
CATEGORIES:Verification
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20261117T110000
DTEND;TZID=America/New_York:20261118T170000
DTSTAMP:20260728T013742Z
CREATED:20260722T152723Z
LAST-MODIFIED:20260728T013742Z
UID:10000005-1794913200-1795021200@2rtp.com
SUMMARY:UVM Fundamentals
DESCRIPTION:Workshop Description \nHands‑on introduction to UVM testbench architecture\, reusable components\, and verification strategies for FPGA/SoC designs.  \nThe emphasis is on:  \n\nIntroducing structured verification planning and coverage‑driven methodology \n\n\nCovers complete UVM architecture\, including agents\, sequences\, and phasing \n\n\nBuilds practical skills in drivers\, monitors\, scoreboards\, and TLM connections \n\n\nExplains factory\, configuration database\, and testbench reuse mechanisms \n\n\nImplements constrained random stimulus and layered sequence libraries \n\n\nIntegrates UVM Register Abstraction Layer (RAL) for register‑level verification \n\n\nApplies functional coverage and regression strategies for closure \n\n\nIncludes hands‑on labs targeting real SoC subsystems (AXI\, Avalon\, DMA\, interrupts\, CDC)\n\nWorkshop Duration: 2 days
URL:https://2rtp.com/workshop/uvm-fundamentals/
CATEGORIES:Verification
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BEGIN:VEVENT
DTSTART;TZID=America/New_York:20261208T110000
DTEND;TZID=America/New_York:20261209T170000
DTSTAMP:20260728T013815Z
CREATED:20260722T153424Z
LAST-MODIFIED:20260728T013815Z
UID:10000007-1796727600-1796835600@2rtp.com
SUMMARY:UVM Advanced
DESCRIPTION:Workshop Description \nAdvanced UVM techniques for complex SoC FPGA verification\, integrating formal methods\, high‑performance testbenches\, and real‑world subsystem validation.  \nThe emphasis is on:  \n\nDeepening UVM expertise with scalable\, production‑grade verification architectures \n\n\nDesigns complex testbench topologies for SoC FPGA (HPS\, fabric\, interconnects) \n\n\nImplements advanced sequencing\, reuse\, and multi‑agent coordination strategies \n\n\nExtends RAL usage for comprehensive register and memory verification \n\n\nIntegrates SVA and formal verification into UVM‑based workflows \n\n\nApplies coverage‑driven methodologies with advanced closure strategies \n\n\nOptimizes simulation performance and prepares environments for emulation \n\n\nCovers real‑world IP (PCIe\, EMIF\, bridges) and subsystem‑level verification\n\nWorkshop Duration: 2 days
URL:https://2rtp.com/workshop/uvm-advanced/
CATEGORIES:Verification
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